EPM3032ATC44-7N

Programmable Logic Device, TRAY, –0.5 to 4.6 V

Rated 5 Rating 5 | reviews | Write a review

Price:: US $0.56~2.20 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
	US $0.56~2.20

PartNumber:: EPM3032ATC44-7N

Brand:: Altera Corporation - ALTR | Pack: DIP | D/C: 10+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

Place Order via Escrow Service

Sold By

Mr. Teven's store

(China (Mainland))

add to my favourite

100% Positive feedback

Detailed seller ratings

Visit Store

Contact Now

Esrcow Service

Place orders confidently and securely via it

Safe payments
Quick and easy transactions
Free service charges

Learn More >>

Previous Next

Products Upload time: 2011-07-24

From Other Seller

Part Number:EPM3032ATC44-7N
US $0.56 - 2.20
A50L-0001-0175

US $100.00 - 100.00 / Piece
(0) Remove
HCPL-7800A

US $2.50 - 4.10 / Piece
(0) Remove
Quantity:

piece

Product Summary

The EPM3032ATC44-7N is a low–cost, high–performance Programmable Logic Device based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EPM3032ATC44-7N operates with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. The EPM3032ATC44-7N in the –4, –5, –6, –7, and –10 speed grades is compatible with the timing requirements of the PCI Special Interest Group (PCI SIG).

Parametrics

EPM3032ATC44-7N absolute maximum ratings: (1)Supply voltage: –0.5 to 4.6 V With respect to ground; (2)DC input voltage: –2.0 to 5.75 V; (3)DC output current, per pin: –25 to 25 mA; (4)Storage temperature No bias: –65 to 150 ℃; (5)Ambient temperature Under bias: –65 to 135 ℃; (6)Junction temperature PQFP and TQFP packages, under bias: 135 ℃.

Features

EPM3032ATC44-7N features: (1)High.performance, low.cost CMOS EEPROM.based programmable logic devices (PLDs) built on a MAXR architecture; (2)3.3-V in-system programmability (ISP) through the built.in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with; (3)advanced pin-locking capability: ISP circuitry compliant with IEEE Std. 1532; (4)Built.in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990; (5)Enhanced ISP features: Enhanced ISP algorithm for faster programming, ISP_Done bit to ensure complete programming, Pull-up resistor on I/O pins during in.system programming; (6)High.density PLDs ranging from 600 to 10,000 usable gates; (7)4.5.ns pin.to.pin logic delays with counter frequencies of up to 227.3 MHz.