Product Summary

The CPLD EPM240T100C5N contains a two-dimensional row- and column-based architecture to implement custom logic. Row and column interconnects provide signal interconnects between the logic array blocks (LABs). LABs are grouped into rows and columns across the EPM240T100C5N. The MultiTrack interconnect provides fast granular timing delays between LABs. The EPM240T100C5N I/O pins are fed by I/O elements (IOE) located at the ends of LAB rows and columns around the periphery of the device. The EPM240T100C5N provides a global clock network. The global clock network consists of four global clock lines that drive throughout the entire device, providing clocks for all resources within the device.

Parametrics

EPM240T100C5N absolute maximum ratings: (1)VCCINT Internal supply voltage: –0.5 to 4.6 V; (2)VCCIO I/O supply voltage: –0.5 4.6 V; (3)VI DC input voltage: –0.5 to 4.6 V; (4)IOUT DC output current, per pin: –25 to 25 mA; (5)TSTG Storage temperature No bias: –65 to 150 ℃; (6)TAMB Ambient temperature Under bias: –65 to 135 ℃; (7)TJ Junction temperature TQFP and BGA packages: 135 ℃.

Features

EPM240T100C5N features: (1)Low-cost, low-power CPLD; (2)Instant-on, non-volatile architecture; (3)Standby current as low as 25 μA; (4)Provides fast propagation delay and clock-to-output times; (5)Provides four global clocks with two clocks available per logic array block (LAB); (6)UFM block up to 8 Kbits for non-volatile storage; (7)MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V or 1.8 V; (8)MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels; (9)Supports hot-socketing.

Diagrams

EPM240T100C5N block diagram

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(USD)		 Quantity
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