TLK3138ZDU

Product Summary

The TLK3138ZDU is an eight channel serial transceiver. It is compliant with the 10Gbps Ethernet XAUI specification. The TLK3138ZDU provides 10 Gbps high-speed bi-directional point-to-point data transmission. The primary application of this device is in backplanes and front panel connections requiring dual/redundant 10Gbps connections over controlled impedance media of approximately 50W. The transmission media can be printed circuit board (PCB) traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling into the lines. The applications of the TLK3138ZDU include 10 Gigabit Ethernet Servers and Routers.

Parametrics

TLK3138ZDU absolute maximum ratings: (1)DVDD, AVDD, VTT, VREF: -0.3 to 1.5V; (2)Supply voltage(2) VDDQ -0.3 to 1.6V; (3)VDDP, VDDO, VDDM: -0.3 to 3 V; (4)VI Input Voltage, LVCMOS: -0.3 to Supply 3; HSTL CLASS 1: -0.3 to 2V; (5)Storage temperature: -65 to 150℃; (6)Electrostatic Discharge, HBM: 2 KV; CDM: 500 V; (7)Characterized free-air operating temperature range: 0 to 70℃.

Features

TLK3138ZDU features: (1)Eight Channel 3.125 Gbps Transceiver; (2)Contains Two Complete IEEE P802.3ae-2002 10 Gbps Ethernet XGXS(XAUI) Compliant Cores; (3)XAUI (Serial side) Channel Redundancy ModeSupport: Fast Switching from Primary to Secondary XAUI/Channel with Provisionable Error Character or Local Fault Code Insertion at Switch Time ; (4)XGMII (Parallel side) Channel Redundancy (1) XGMII Extender Sublayer Mode Support: Fast Switching from Primary to Secondary XGMII/Channel with Provisionable Error Character or Local Fault; (5)Code Insertion at Switch Time; (6)Serial Side Transmit Pre-emphasis and Receive Adaptive Equalization to Allow Extended Backplane Reach; (7)Selectable Full Duplex Serial Side Retimer Mode; (8)Full Datapath Loopback Capability (Serial/Parallel Side); (9)Support PRBS 27-1 and 223-1 Generate/Verify. Support Standard Defined CJPAT, CRPAT, High Frequency, Low Frequency, and Mixed; (10)Frequency Testing; (11)XGMII: HSTL Class 1 I/O with On-chip 50-W Termination on Inputs/Outputs (1.5-V Power Supply); (12)XGMII: Support Receive (Output) Aligned/Centered Timing Modes, and Transmit (Input) Source Centered Mode; (13)Supports Jumbo Packet (9600 byte maximum) Operation; (14)Align Character Skew Support of 30 bit Times at Chip Pins; (15)Dual MDIO: IEEE 802.3ae Clause 45 Compliant Management Data Input / Output Interface (1.2-V and 2.5-V I/O); (16)1.2-V Core, 1.5-V HSTL I/O Supply, and 2.5-V LVCMOS and Bias Supply; (17)JTAG: IEEE 1149.1 Test Interface ±200 ppm Clock Tolerance in XAUI Transmit and Receive Datapaths; (18)Diagnostic LED Output Interface; (19)130-nm CMOS Technology; (20)Package: PBGA 484, 23×23mm, 484 ball, 1mm Pitch; (21)2.42 W Typical Power Dissipation (Dual XAUI Mode, Input HSTL Termination Disabled); (22)Commercial Ambient Operating Temp(0℃ to 70℃).

Diagrams